/**
 * *****************************************************************
 * @file    adt3102.h
 * @version 1.0.0
 * @date    2022-02-10
 * @brief  
 *                 Copyright (c) 2022, Andar Technologies Inc.
 *                           www.andartechs.com 
 *
 * *****************************************************************
 */
#ifndef __ADT3102__H
#define __ADT3102__H
#include "adt3102_adc.h"


/*----------------------------- define ---------------------------------------*/
/*----------------------------- section 1: System -----------------------------------------*/
/********************************************
 1.1 MIMO setting
*********************************************/
#ifndef  TXRXTYPE
#define  TXRXTYPE           TX2RX2
#endif

#ifndef  CHIRPS_TX_MODE
#define  CHIRPS_TX_MODE     CONTINUE_CHIRPS_MODE
#endif

//TX1RX1:   single Tx and single Rx
//TX1RX2:   single Tx and double Rx
//TX2RX2:   double Tx and double Rx
// ADT6101 supports TD_MIMO only
#define  TX1RX1    (1)
#define  TX1RX2    (2)
#define  TX2RX2    (4)

#define TX0               (1)
#define TX1               (2)

#ifndef  PRIMARY_TDD_CH
#define  PRIMARY_TDD_CH           TX0
#endif

#define PA1_ONLY          (0)


#if TXRXTYPE == TX2RX2
#define MIMO              (1)          // 1: MIMO enable
#else
#define MIMO              (0)
#endif


/********************************************
 1.2 CHIRP sending setting
*********************************************/
//CONTINUE_CHIRPS_MODE: chirps in one frame transmitted in continuous mode, 
//                      without delay in between
//SINGLE_CHIRPS_MODE:   chirps in one frame transmitted in single mode, 
//                      with some delay in between
#define  CONTINUE_CHIRPS_MODE     (1)
#define  SINGLE_CHIRPS_MODE       (2)

#if CHIRPS_TX_MODE == SINGLE_CHIRPS_MODE
    #if TXRXTYPE == TX1RX1
        #define CHIRP_NUM_FMCW_CONFIG (1)
    #elif TXRXTYPE == TX1RX2
        #define CHIRP_NUM_FMCW_CONFIG (1)
    #elif TXRXTYPE == TX2RX2
        #define CHIRP_NUM_FMCW_CONFIG (2)
    #else
        #define CHIRP_NUM_FMCW_CONFIG (1)
    #endif
#elif CHIRPS_TX_MODE == CONTINUE_CHIRPS_MODE
    #if TXRXTYPE == TX1RX1
        #define CHIRP_NUM_FMCW_CONFIG (CHIRP_NUM)
    #elif TXRXTYPE == TX1RX2
        #define CHIRP_NUM_FMCW_CONFIG (CHIRP_NUM)
    #elif TXRXTYPE == TX2RX2
        #define CHIRP_NUM_FMCW_CONFIG (CHIRP_NUM*2)
    #else
        #define CHIRP_NUM_FMCW_CONFIG (CHIRP_NUM)
    #endif
#else
    #error "error"
#endif


/* v1.5.0, If you comment on this macro definition in this
    version, there will be a compilation error. */
#define COMPATIBLE

/* Debug define e.g.,printf, output result, analog IF sign enbuffer
<q.0> Enable debug mode */
#define DEBUGMODE               0
#define PRINTF_TF               1

/* High clock */
#define HIGH_CLOCK_50M          1
#define HIGH_CLOCK_125M         0

#define UART0_PRINTF
//#define UART1_PRINTF

#define HIGH_CLOCK              HIGH_CLOCK_125M

/*------------------------- RF/IF ------------------------*/
/*
    FMCW config (76~80)
    Default: 76G(Uint:GHz)
*/
#define FSTART                  75
/*
    FM(0~4000)
    Default: 4000(Uint:MHz)
*/
#define FM                      4000
/*
    CHIRP_NUM(0~256)
    Default: 32(CHIRP_NUM)
*/

#define CHIRP_NUM               32
#define CHIRP_NUM_LOG2          5

              
#define CHIRP_T0                96   /* Unit: us */  //960 //1920
#define CHIRP_T1                96   /* Unit: us */
#define CHIRP_T2                0    /* Unit: us */

//period: unit: us
#define CHIRP_PERIOD        (CHIRP_T0+CHIRP_T1+CHIRP_T2)

// chirp period, unit:  macro second 20Hz
#define CHIRP_PERIOD_SINGLE (3125)

/* please make sure g_tx0En=g_tx1En=1.  g_PaGain0 and g_PaGain0 not be zero. */
//#define TD_MIMO
/* please make sure g_tx0En=g_tx1En=1.  g_PaGain0 and g_PaGain0 not be zero. */
//#define BP_MIMO
/* in cascade appliaction, and as a master */
//#define CASCADE_MASTER
/* in cascade appliaction, and as a slave */
//#define CASCADE_SLAVE

#define ADC_SAMPLE_RATE         ADC_8P3M    /* ADC_16P6M: 16.667mhz.   ADC_8P3M: 8.333mhz */
#define REMOVE_FIRST_CHIRP      0           /* 2db better */
#define RANGE_MIN               3
#define RANGE_MAX               256
#define DOWN_SAMPLE             0           /* actual down sample rate = 1/(DOWN_SAMPLE+1). */
#define SAMPLE_POINT            256
#define RANGE_STEP              (10.0)        /* 5.86cm for 96us . 4.03cm for 66us  4.76cm for 78us */
#define SPEED_STEP              56.37       /* cm/s */
#define WN_BYPASS               1
#define FRAME_PERIOD            100000       /* Unit: us */
#define SAGC_EN                 0
#define TF_ENABLE               0
#define FRAME_LOWPOWER          1
#define CHIRP_LOWPOWER          0
#define PRINT_DEBUG_EN          0
#define ADT_TF_TYPE             0x0A00

//low noise mode during RF switch
#define DISABLE_LOW_NOISE   (1)

// frame period  ENBALE,
#define ENBALE_FRAME_PERIOD (1)

/*-------------------- memory address --------------------*/

/*
    [0x20008000-0x2001bfff] size: 2KB
    [0x2001c000-0x20030000] size: 2KB
*/
// ADC sampling buffer address
#define ADC_CH0_DATA_ADDR           (0x20008000)
#define ADC_CH1_DATA_ADDR           (0x2001c000)


/*--------------------------- ADC ------------------------*/
/* FFT buffer start address input for 1st half */
#define FFT_BUF_HF1             0x20030000
/* FFT buffer start address input for 2nd half */
#define FFT_BUF_HF2             0x20030000 + 256*4

#if (ADC_SAMPLE_RATE == ADC_16P6M)
  #define SAMPLE_END_NUM  ceil((CHIRP_T1+CHIRP_T2)*16.666)
  #define INTERVALNUM     floor((CHIRP_T0+CHIRP_T1+CHIRP_T2)*1000/60)	
#else
  #define SAMPLE_END_NUM  ceil((CHIRP_T1+CHIRP_T2)*8.333)
  #define INTERVALNUM     floor((CHIRP_T0+CHIRP_T1+CHIRP_T2)*1000/120)
#endif

#if 0
// 512 1
#define FIRREG0  ((0<<13)     +0x1fff)
#define FIRREG1  ((1<<13)     +0x1) 
#define FIRREG2  ((0x1ffd<<13)+0x1fff)
#define FIRREG3  ((5<<13)     +0x0)
#define FIRREG4  ((0x1ffa<<13)+0x3)
#define FIRREG5  ((0x4<<13)   +0x1ff7)
#define FIRREG6  ((0x3<<13)   +0x10)
#define FIRREG7  ((0x1fef<<13)+0x1fea)
#define FIRREG8  ((0x25<<13)  +0x16)
#define FIRREG9  ((0x1fc6<<13)+0x1ff6)
#define FIRREG10 ((0x46<<13)  +0x1fee)
#define FIRREG11 ((0x1fc2<<13)+0x40)
#define FIRREG12 ((0x11<<13)  +0x1f83)
#define FIRREG13 ((0x58<<13)  +0xc0)
#define FIRREG14 ((0x1ec2<<13)+0x1f03)
#define FIRREG15 ((0x4ef<<13) +0x129)
#define FC       (0x6c8)
#endif

#if 0
/* Dn = 2 */
#define FIRREG0   0x1FFF
#define FIRREG1   0x2001
#define FIRREG2   0x3FFBFFF
#define FIRREG3   0xA000
#define FIRREG4   0x3FF4003
#define FIRREG5   0x9FF7
#define FIRREG6   0x6010
#define FIRREG7   0x3FDFFEA
#define FIRREG8   0x4A016
#define FIRREG9   0x3F8DFF6
#define FIRREG10  0x8DFEE
#define FIRREG11  0x3F84040
#define FIRREG12  0x23F83
#define FIRREG13  0xB00C0
#define FIRREG14  0x3D85F03
#define FIRREG15  0x9DE129
#define FIRREG16  0x6C8
#endif

#if 1
#define FIRREG0   0x0
#define FIRREG1   0x0
#define FIRREG2   0x0
#define FIRREG3   0x0
#define FIRREG4   0x0
#define FIRREG5   0x0
#define FIRREG6   0x0
#define FIRREG7   0x0
#define FIRREG8   0x0
#define FIRREG9   0x0
#define FIRREG10  0x0
#define FIRREG11  0x0
#define FIRREG12  0x0
#define FIRREG13  0x0
#define FIRREG14  0x0
#define FIRREG15  0x0
#define FIRREG16  0xfff
#endif


#if 0
//f = [0 0.1 0.12 1]  8
#define FIRREG0  0x3FFBFFD
#define FIRREG1  0x3FFDFFE
#define FIRREG2  0x3FFF
#define FIRREG3  0xE004
#define FIRREG4  0x1A00A
#define FIRREG5  0x1C00F
#define FIRREG6  0xA00B
#define FIRREG7  0x3FDFFFB
#define FIRREG8  0x3FA5FE0
#define FIRREG9  0x3F83FC7
#define FIRREG10 0x3F9DFC2
#define FIRREG11 0x13FE5
#define FIRREG12 0xE4039
#define FIRREG13 0x1E80B2
#define FIRREG14 0x2D6133
#define FIRREG15 0x364197
#define FIRREG16 0x1BC
#endif


#if 0
//f = [0 0.05 0.06 1]  16
#define FIRREG0  0x3FFBFFD
#define FIRREG1  0x3FF9FFC
#define FIRREG2  0x3FF5FFB
#define FIRREG3  0x3FF1FF9
#define FIRREG4  0x3FEFFF7
#define FIRREG5  0x3FF3FF8
#define FIRREG6  0x1FFC
#define FIRREG7  0x18005
#define FIRREG8  0x3E015
#define FIRREG9  0x7002B
#define FIRREG10 0xAE047
#define FIRREG11 0xF0067
#define FIRREG12 0x132089
#define FIRREG13 0x16C0A8
#define FIRREG14 0x1960C1
#define FIRREG15 0x1AE0D2
#define FIRREG16 0xD8
#endif

#if 0
//f = [0 0.01 0.015 1]  64
#define FIRREG0  0x6003
#define FIRREG1  0x8003
#define FIRREG2  0xA004
#define FIRREG3  0xE006
#define FIRREG4  0x14008
#define FIRREG5  0x1A00B
#define FIRREG6  0x2200F
#define FIRREG7  0x2A013
#define FIRREG8  0x32017
#define FIRREG9  0x3A01B
#define FIRREG10  0x4201F
#define FIRREG11  0x48022
#define FIRREG12  0x4E026
#define FIRREG13  0x52028
#define FIRREG14  0x5602A
#define FIRREG15  0x5802C
#define FIRREG16  0x2C
#endif

#define FC        (FIRREG16 | (DOWN_SAMPLE << fir_cof_sample_rate_down_sample_rate_shift))

/*--------------------------- CFAR -----------------------*/
#define CFAR_ADDR 0x40024000


/*----------------------------- typedef --------------------------------------*/
typedef enum
{
    ADT_IDLE,
    ADT_SCAN,
    ADT_SLEEP
}ADTStateTypedef;


#endif
